This invention pertains to digital circuitry, and more particularly to asynchronous digital circuitry in which data is moved from a register or storage element.
FIG. 1 is a block diagram of a typical prior art circuit which includes register 102 and register 105. Register 102 receives input data via bus 101 which is loaded into register 102 in response to the clock signal applied to clock input lead 104 of register 102. Once loaded, this data is available from register 102 on output bus 103. This data is fed from bus 103 to, for example, register 105. This data is loaded into register 105 in response to a store signal applied to the clock input lead 107 of register 105. Once loaded into register 105, the data is available on output bus 106.
A problem with the typical prior art circuit of FIG. 1 is that if the store signal applied to input lead 107 of register 105 is asynchronous to the clock signal applied to clock input lead 104 of register 102, register 105 will randomly (with respect to the clock signal applied to clock input lead 104) sample the data on data bus 103 for storage in register 105. Thus, this sampling by register 105 may occur while register 102 is being updated, during which time the output data from register 102 available on bus 103 is not valid. In this event, register 105 stores invalid data, clearly an undesirable result.